Integrated circuit memory devices can be volatile or non-volatile memory devices. In a volatile memory device, for example, a dynamic random access memory (DRAM) and a synchronous random access memory (SRAM), data may be lost when power is cut off. In a non-volatile memory device, for example, a flash memory, data is retained when power is cut off.
Typically, flash memory cells have a gate pattern that includes a gate insulating layer, a floating gate, a dielectric layer and a control gate that are sequentially stacked on a substrate. The flash memory cells may use tunneling to program and/or erase data therein. When a tunnel is present in the gate insulating layer an operating voltage that is higher than a power supply voltage may be necessary. Accordingly, conventional flash memory devices may include a booster that enables the flash memory device to apply enough voltage to program and/or erase data.
Recently, a new-type of non-volatile memory device, for example, a phase changeable memory device, has been proposed to replace or supplement existing non-volatile memory devices. Referring now to FIG. 1, an equivalent circuit diagram of a unit cell of conventional phase changeable memory devices will be discussed. As illustrated in FIG. 1, the phase changeable memory cell includes an access transistor Ta and a variable resistor C. The variable resistor C includes a lower electrode, an upper electrode and a phase changeable material layer disposed therebetween. The upper electrode of the variable resistor C is connected to a plate electrode PL. The access transistor Ta includes a source region, a drain region and a gate electrode. The source region is connected to the lower electrode of the variable resistor C and the drain region is spaced apart from the source region. The gate electrode of the access transistor Ta is located over a channel region between the source and drain regions. The gate electrode and drain region of the access transistor Ta are connected to a word line WL and a bit line BL, respectively. Accordingly, the equivalent circuit diagram of the phase changeable memory device is similar to that of a DRAM cell. However, properties of the phase changeable material layer are different from a dielectric layer used in a DRAM cell. For example, the phase changeable material layer may have two stable states based on a temperature.
Referring now to FIG. 2, a graph illustrating steps of programming and erasing the phase changeable memory cell will be discussed. The “X” axis represents a time T and the “Y” axis represents a temperature TMP of the phase changeable material layer. As illustrated in FIG. 2, when the phase changeable material layer is heated at a temperature higher than a melting temperature Tm for a first duration T1 and cooled, the phase changeable material layer changes into an amorphous state (curve 1). However, when the phase changeable material layer is heated at a temperature between the melting temperature Tm and a crystallization temperature Tc for a period between the first duration T1 and a second duration T2 and cooled, the phase changeable material layer changes into a crystalline state (curve 2). The second duration T2 is typically longer than the first duration Ti. In this case, a resistivity of the phase changeable material layer in the amorphous state is typically larger than that in the crystalline state. Thus, by detection of an amount of current flowing through the phase material layer during a read cycle, it may be unable to discriminate between data having a value of “0” and data having a value of “1” stored in the phase changeable memory cell. The phase changeable material layer generally includes a compound material layer such as germanium (Ge), tellurium (Te) and antimony (Sb) (GTS).
Referring now to FIG. 3, a plan view illustrating a portion of a cell array of conventional phase changeable memory devices will be discussed. As illustrated in FIG. 3, a plurality of active regions 10 are two-dimensionally disposed on an integrated circuit substrate. A plurality of gate lines 20 are disposed crossing over the active regions 10. The gate lines 20 correspond to word lines. The active regions 10 are disposed beneath a plurality of gate lines 20, for example, two gate lines 20. As illustrated, the active regions 10 are divided into three regions by the plurality of gate lines 20. A portion of the active region 10 between the plurality of gate lines 20 may correspond to a common drain region 11. Portions of the active region 10 on either side of the common drain region 11 may correspond to source regions 12 and 13. The common drain region 11, one of the source regions 12 and 13 and the gate line 20 provide a transistor. In other words, each active region 10 includes two unit cells.
The common drain region 11 is electrically connected to bit line 30 through bit line contact hole 25. A plurality of bit lines 30 cross over the gate lines 20. A phase changeable material pattern 40 is disposed over the source region. The phase changeable material pattern 40 is electrically connected to the source regions 12 and 13 under the phase changeable material pattern 40, through a heater plug (not shown) in a contact hole 35. The phase changeable material pattern 40 is electrically connected to the plate electrode (not shown) over the phase changeable memory device.
The phase changeable material pattern 40 may be formed of GTS and the heater plug may be formed of titanium nitride (TiN). To program desired data into the phase changeable pattern 40, the density of current flowing through the heater plug may be increased. Thus, a diameter of the heater plug may be decreased and a channel width A of the transistor may be increased to provide increased current to the heater plug. Accordingly, an area B of a cell or cells may be increased to accommodate the needed increased current capacity of the transistor. Accordingly, improved phase changeable integrated circuit devices may be desired.